This application claims priority from Korean Patent Application No. 2003-33347, filed on May 26, 2003, the contents of which are incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor memory device including capacitor lower electrodes, and a method of manufacturing the same.
2. Description of the Related Art
As there is an increase in the integration density of semiconductor devices, the design rule decreases and thus the area occupied by each memory cell in a semiconductor memory device is scaled down. In a dynamic random access memory (DRAM), a capacitor used in a memory cell occupies a smaller area but requires the minimum capacitance enough to provide generally allowable data input and output characteristics and data reproduction characteristics. Thus, to manufacture a capacitor that maintains the minimum capacitance in a reduced space, a variety of lower electrodes having a 3-dimensional shape and an increased height have been proposed. Among them, a cylindrical lower electrode is broadly used because it can highly increase the effective area of a capacitor. In particular, more attention is paid to a capacitor-over-bit line (COB)-type cylindrical lower electrode.
With a reduction in the memory cell area, bottom critical dimension (CD) of a cylindrical lower electrode of a capacitor substantially decreases. Thus, the lower electrode is highly likely to fall down. Because the distance between adjacent lower electrodes is very narrow due to the reduced cell area, merely the slight leaning of the lower electrode may lead it to contact the next lower electrode, thereby causing a twin bit failure. To prevent the leaning of the lower electrode, the bottom CD of a capacitor should be increased or the height of the lower electrode should be decreased. However, if a desired design rule is predetermined, the bottom CD cannot be increased greater than the design rule. Also, if the height of the lower electrode is reduced, a sufficient capacitance cannot be obtained.
Recently, a variety of attempts have been made to change arrangement or sectional shape of lower electrodes to overcome the foregoing restrictions. However, in these cases, an active region of a semiconductor substrate can deviate from the position of a lower electrode. Thus, securing a sufficient contact margin for electrical connection of the lower electrode with the active region has been difficult.
On the other hand, a buried contact (BC) plug, i.e., a storage node contact, formed for electrical connection of an active region with a lower electrode should have has an appropriate size to reduce contact resistance. However, in a COB-type structure, the distance between the BC plug and a bit line is too short to secure a sufficient misalignment margin therebetween. For this reason, the BC plug and the bit line are formed by a self-aligned contact (SAC) process using an etch selectivity between oxide and nitride. When the SAC process is performed to form a contact, to secure a sufficient contact margin for electrical connection between the active region and the lower electrode, the design should be appropriately modified depending on the layout of the contact. In particular, if a hole-type contact is to be formed using the SAC process, it is difficult for a conventional method to provide a sufficient contact margin for electrical connection of an active region with a lower electrode.